The present invention relates to a folding A/D (analog/digital) converter (hereinafter referred to as an “ADC”), and an error correction circuit used in the folding ADC.
As described in a non-patent document (Kazuhide NANBA et al., “High Speed Low-Power Consumption A/D Converter”, IEICE Technical Report, The Institute of Electronics, Information, and Communication Engineers, September 1999, ICD 99–161, pp. 1–8), a folding ADC performs analog/digital conversion by using a folding technology. As shown in FIG. 6, a folding ADC 30 includes an upper ADC circuit 32 for converting upper bits, a folding circuit 34 for converting lower bits, and a lower ADC circuit 36 for converting lower bits. Here, as the upper ADC circuit 32 and the lower ADC circuit 36, for example, a parallel comparison type (flash type) ADC circuit is used.
For example, when the upper ADC circuit 32 is two bits long, in the upper ADC circuit 32, three comparators are used in which three-level voltages V1, V2, and V3, which are obtained by dividing into four portions the section between the maximum value Vmax and the minimum value Vmin of an input voltage Vin of an analog signal, are each used as a reference voltage. In the upper ADC circuit 32, in each of the three comparators, by simultaneously comparing the input voltage Vin of an analog signal with each of the corresponding reference voltages V1, V2, and V3, two upper bits of a digital signal corresponding to the input voltage Vin of an analog signal are obtained.
The folding circuit 34 generates a folding signal having a voltage required for A/D conversion in the lower ADC circuit 36. As shown in FIG. 6, the output voltage Vout of the folding circuit 34 has output characteristics such that the voltage is folded in sequence at each of the corresponding reference voltages V1, V2, and V3 of the upper ADC circuit 32 with respect to the input voltage Vin of an analog signal.
In the lower ADC circuit 36, A/D conversion is performed based on the voltage level of the folding signal output from the folding circuit 34. For example, when the lower ADC circuit 36 is two bits long, in the lower ADC circuit 36, three-level reference signals, which are obtained by dividing into four portions the section between the maximum value and the minimum value of the output voltage of the folding signal, are used. In each of the three comparators, by simultaneously comparing the folding signal with each of the corresponding reference signals, two lower bits of a digital signal corresponding to the input voltage Vin of an analog signal are obtained.
In the folding ADC 30, by separately performing the upper bit conversion and the lower bit conversion, the number of comparators can be reduced, and thus a lower power consumption can be achieved. Furthermore, since the upper bit conversion and the lower bit conversion can be performed independently and simultaneously, the folding ADC 30 is suitable for achieving a higher speed.
However, as shown in FIG. 7, in the actual waveform of the folding signal, characteristics generally deteriorate in the peak portion and the valley portion of the folding signal when compared to an ideal waveform, indicated by the dotted line in FIG. 7. As such, the conversion accuracy of the lower bits deteriorates.
In order to reduce this deterioration, for example, when the lower ADC circuit 36 is two bits long, a technique is used in which four folding signals, whose output voltages of the lower ADC circuit 36 are shifted for each voltage of the analog signal by one bit with respect to the input voltage Vin of the analog signal, are generated, and in each of the four comparators, each voltage level of the four folding signals is simultaneously compared with the center level (zero-cross detection), thereby obtaining lower bits.
In the folding ADC 30, the overall conversion result is obtained by adding (combining) the conversion result of the upper bits by the upper ADC circuit 32 and the conversion result of the lower bits by the lower ADC circuit 36. However, in the technique described above, since the conversion of the upper bits by the upper ADC circuit 32 and the conversion by the folding circuit 34 and the lower ADC circuit 36 are performed independently, a mismatch may occur between them.
For example, as shown in FIG. 8, when it is assumed that the input voltage of an analog signal is at an “x” level, there are cases in which the conversion result of the upper bits becomes “01”, the conversion result of the lower bits becomes “00”, and the overall conversion result becomes “0100”. However, when the conversion result of the lower bits is considered as a reference, the overall conversion result should become “1000”. Such a mismatch between the conversion result of the upper bits and the conversion result of the lower bits can occur because of variations in devices forming the folding circuit 34 and the comparators.
As one means for solving this problem, an error correction circuit is known. FIG. 9 is a conceptual view illustrating the operation of an error correction circuit used in a two-step flash type ADC for two upper bits and two lower bits. As a result of using the error correction circuit illustrated in FIG. 9, for example, when “10” is obtained as the conversion result of the upper bits, in the lower ADC circuit, a conversion of the lower bits is performed in a range wider than the range of “10”, which is the conversion result of the upper bits, and the conversion result of the upper bits is corrected in accordance with the conversion result of the lower bits.
In the case of an ADC with two upper bits and two lower bits, the number of necessary comparators is ideally a total of 6, that is, three for the upper bits and three for the lower bits. The number of comparators is smaller than 15, which is generally required when a 4-bit flash type ADC is formed. In the above-described example, as a result of performing error correction, a total of 10 comparators (◯ in FIG. 9 indicates a comparator for a lower ADC circuit, ● and indicates a comparator for an error correction circuit), that is, three for the upper bits and seven for the lower bits, are required. Furthermore, a circuit for incrementing or decrementing by 1 the upper conversion result is necessary.
In the above-described example, an error correction circuit of a flash type ADC is described, and in the folding ADC, the identical error correction circuit is also necessary. However, as described above, in the conventional error correction circuit, there is a problem in that the circuit size becomes too large.